1. Field of the Invention
This invention relates to semiconductor structures, and in particular to field effect transistor (FET) devices incorporating depleted zones in the gate conductor along the corner region of the FET to increase the threshold voltage of the corner device.
2. Description of Related Art
Contemporary CMOS devices employ field effect transistors (FET) which are adjacent to or bounded by trenches such as shallow trench isolation (STI). As the widths of these devices are made smaller, unwanted effects originating at the corner device i.e., the channel region under gate conductor at the corners of the trenches, become more significant. It has been found that the electric field in the gate conductor near the trench corner may become enhanced, which leads to a reduction of the threshold voltage of the channel in that region, compared to the threshold voltage of the channel under the planar portion of the gate away from the corner. This lower threshold voltage provides a parallel path for current conduction which has different turn-on characteristics and adversely affects the performance of the device.
Attempts have been made to solve this problem in various ways, for example, reducing STI pull down, increasing the corner rounding at the edges of the STI as described in U.S. Pat. Nos. 5,578,518 and 5,647,775, or increasing oxide thickness over the corner region as described in U.S. Pat. Nos. 5,387,540 and 5,436,488. While such techniques have been found to reduce the threshold voltage of the corner device, they provide other problems such as increasing the complexity of manufacturing requirements or requiring an undesirable increase in the thickness of layers. Some of the prior art techniques have caused an increase in voltage threshold away from the corners as well.
Accordingly, a need exists for a semiconductor structure which increases threshold voltage at isolation corners which may be fabricated with improved reliability and fewer performance problems.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a structure and method for increasing threshold voltage near the corner of isolation regions in a semiconductor structure, particularly FETs.
It is another object of the present invention to provide a method and system which reduces the complexity of prior manufacturing methods for increasing threshold voltage in a corner device.
A further object of the present invention is to provide a method and system which makes modeling of a field effect transistor simpler and more reliable.
Another object of the present invention is to provide a more voltage tolerant semiconductor structure to be used for mixed-voltage peripheral input/output circuitry, analog applications and electrostatic discharge (ESD) applications.
Yet another object of the present invention is to provide a structure which is more tolerant to electrical overstress (EOS) and ESD.